NAME¶

Perlilog - Verilog environment and IP core handling in Perl

SYNOPSIS¶

  use Perlilog;

DESCRIPTION¶

The project is extensively documented in Perlilog's user guide, which can be downloaded at the project's home page, <http://www.opencores.org/perlilog/>, or at my own: <http://www.billauer.co.il/perlilog.html>.

In wide terms, Perlilog is a Perl environment for Verilog code manipulation. It supplies the Perl programmer with several strong tools for managing Perl modules and connecting between them.

Originally, Perlilog was intended for integration of Verilog IP cores, but it's useful for the following tasks as well:

• Scripts that generate Verilog code automatically
• "Hook-up" of modules: Assigning pins, connecting to ASIC pads, etc.
• Automatic generation of buses and bus controllers, with a variable number of members and parametrized arbitration rules
• Automatic generation of bridges when needed to interface between different bus protocols

ACKNOWLEDGEMENTS¶

This project would not exist without the warm support of Flextronics Semiconductors in Israel, and Dan Gunders in particular.

AUTHOR¶

Eli Billauer, <elib@flextronics.co.il>

SEE ALSO¶

The Perlilog project's home page: <http://www.opencores.org/perlilog/>

The author's home page: <http://www.billauer.co.il/>

The Eobj project: <http://www.billauer.co.il/eobj.html>